Room A & Plenary Sessions

Room B

Time (Hanoi)

Oct. 08

7:30-8:30

Registration

8:30-8:50

Opening Session

8:50-9:25

Keynote 1: “Next-Generation IC Security: Resilient Hardware Design and AI-Enabled Forensic Verification”

Prof. Bah-Hwee Gwee, Nanyang Technological University, Singapore

9:25-10:00

Keynote 2: “Enforcing Security in the Supply Chain of Chiplets through Transparency”

Dr. Sylvain Guilley, Cadence Design Systems and Telecom Paris, France

10:00-10:25

Coffee break & Expo

10:25-11:55

Session R1: 5 papers/90 min

Memory, digital systems and testing

Session R2: 5 papers/90 min

AI, IoT & communications 1

12:00-13:20

Lunch

13:30-14:05

Keynote 3: “Practical Non-Destructive Detection: Case Study of Durain, Mangosteen, and Granular Ingredients”

Prof. Kosin Chamnongthai, King Mongkut’s University of Technology Thonburi, Thailand

14:05-14:30

Invited talk 1: Bridging the Gap Between Specification and Reality: Cellular Modem Development and Global Field Testing

Prof. Chaehag Yi, Seoul National University, Korea

14:30-14:55

Coffee break & Expo

14:55-16:07

Session R3: 4 papers/72 min

FPGA and Embedded systems 1

Session R4: 4 papers/72 min

Analog/mixed-signal circuits 1

16:10-17:40

Session R5: 5 papers/90 min

Hardware security and cryptography 1

Session R6: 5 papers/90 min

RF & microwave circuits

18:30-21:00

Gala Dinner

Oct. 09

7:30-8:00

Registration

8:00-8:25

Invited Talk 2: “Open-Source EDA and PDKs in VLSI Design: The Era of Agentic AI, Maturing Ecosystems, and Democratized Silicon”

Prof. Trong-Thuc Hoang, University of Electro-Communications, Japan & Prof. Van-Phuc Hoang, Le Quy Don Technical University, Vietnam

8:25-9:00

Keynote 4: “From Cloud Datacenters to Secure Edge: Review of Compute-in-Memory at EUV/FINFET Era”

Prof. Koichiro Ishibashi, Universiti Teknologi Malaysia Kuala Lumpur (UTMKL), Malaysia

9:00-9:20

Coffee break & Expo

9:20-9:45

Invited talk 3: A Methodology to Derive Security Specifications for Complex Electronic Systems

Sylvain Guilley (Telecom Paris & Cadence Design Systems, France), Ritu-Ranjan Shrivastwa and Ville Yli-Mayry (Cadence Design Systems, France)

9:50-11:38

Session R7: 6 papers/108 min

AI, IoT & communications 2

Session R8: 5 papers/90 min

FPGA and Embedded systems 2

11:50-13:10

Lunch

13:30-14:05

Keynote 5: “Hardware Accelerator Design and Optimization for Functional Encryption”

Prof. Makoto IKEDA, Systems Design Lab (D.lab), Engineering School, The University of Tokyo, Japan

14:05-15:35

Session R9: 5 papers/90 min

AI, Quantum Tech. & Secure Autonomous UxV Systems

Session R10: 4 papers/72 min

Analog/mixed-signal circuits 2

15:35-15:55

Coffee break & Expo

15:55-17:25

Session R11: 5 papers/90 min

Semiconductor Technology

Session R12: 4 papers/72 min

Hardware security and cryptography 2

17:25-17:35

Closing

Oct. 10

9:30-11:00

Committee Meeting

12:00-18:00

Field trip

Room: Hoan Kiem

Room: Ba Dinh

Time (Hanoi)

Oct. 08

7:30-8:30

Registration

8:30-8:50

Opening Session

8:50-9:25

Keynote 1: “Next-Generation IC Security: Resilient Hardware Design and AI-Enabled Forensic Verification”

Prof. Bah-Hwee Gwee, Nanyang Technological University, Singapore

Chair: Prof. Xuan Nam Tran, LQDTU

9:25-10:00

Keynote 2: “Enforcing Security in the Supply Chain of Chiplets through Transparency”

Dr. Sylvain Guilley, Cadence Design Systems and Telecom Paris, France

Chair: Prof. Xuan Tu Tran, VNU ITI

10:00-10:25

Coffee break & Expo

10:25-11:55

Session R1: 5 papers/90 min

Memory, Digital Systems and Testing

Chairs: TBD

A Method for Automated Test Input Generation on Verilator-Generated RISC-V Processor Models

Hiếu Đức Vũ (Vietnam National University Hanoi, Vietnam); Duc-Anh Nguyen and Pham Ngoc-Hung (VNU University of Engineering and Technology, Vietnam)

Algorithm-First NPU Extension via Dual-LLM Workflow

Hsin-I Wu (DeepMentor, Taiwan); You-En Wu (National Yang Ming Chiao Tung University, Taiwan); Ruei-En Wu (Taipei Municipal Heping High School, Taiwan)

PEARL: Credit-Aware Minimal-Adaptive Routing for Mesh NoC

Tien-Hieu Le (Vietnam National University, Hanoi, Vietnam & Microelectronics and Computer Sciences (MCS) Research Center, N.A Viet Nam Ltd, Nghe An, Vietnam); Duy-Hieu Bui (Vietnam National University, Hanoi, Vietnam); Xuan-Tu Tran (VIetnam National University, Hanoi, Vietnam)

Optimization-Guided Traffic Generation: Discovering AXI4 Bottlenecks in Edge CNN Accelerators

Hieu Nguyen (PTIT University, Vietnam); Thao Viet Vuong (Posts and Telecommunications Institute of Technology, Vietnam & PTIT, Vietnam); Huyen Thanh Dao (Posts and Telecommunications Institute of Technology, Vietnam & Gunma University, Vietnam); Dao Anh Vu and Minh-Tuan Le (Posts and Telecommunications Institute of Technology, Vietnam)

A Low-Power and Compact Dynamic Matching and Comparator Circuit with Early Termination for Memory-Centric Computing

Linh Le, Dinh Ha Dao, Kien Trinh Quang, Thi-Hong-Tham Tran and Khoa-Sang Nguyen (Le Quy Don Technical University, Vietnam)

Session R2: 5 papers/90 min

AI, IoT & Communications 1

Chairs: TBD

3D Maneuvering Target Tracking Algorithm Using Unscented Kalman Filter and Particle Filter

Ngo Nhat Anh (Hanoi University of Science and Technology, Vietnam); Hoang Manh Thang (Hanoi University of Science and Technology (HUST), Vietnam)

A Dual-Stream Multi-Scale Fusion Network with YOLO-Style Design for Infrared and Visible Images

Tsung-Han Tsai, Shang-Yin Yu and Bo-En Wei (National Central University, Taiwan)

A Fully-Integrated Raman and Autofluorescence Benchtop System with On-Device AI for Sub-Second Skin Cancer Screening

Hoang ChuDuc (The VNU University of Engineering and Technology & National Technology Innovation Fund, Vietnam)

Action-Responsive Contrastive Network for Efficient Joint-based Hand Gesture Recognition

Duy Tien Le (Vietnam National University, Hanoi, Vietnam); Dinh-Tan Pham (International School, Vietnam National University, Hanoi, Vietnam)

An Always-On Screening and Event-Triggered CNN-LSTM Architecture for Low-Power Wearable Fall Detection

Anh Vu-Duc and Thanh Ta-Van (Posts and Telecommunications Institute of Technology, Vietnam); Bien Nguyen Quang and Duan Luong-Cong (Posts and Telecommunications Institute of Technology (PTIT), Vietnam)

12:00-13:20

Lunch

13:30-14:05

Keynote 3: “Practical Non-Destructive Detection: Case Study of Durain, Mangosteen, and Granular Ingredients”

Prof. Kosin Chamnongthai, King Mongkut’s University of Technology Thonburi, Thailand

Chair: Prof. Duc Hung Le, HCMUS

14:05-14:30

Invited Talk 1: Bridging the Gap Between Specification and Reality: Cellular Modem Development and Global Field Testing

Prof. Chaehag Yi, Seoul National University, Korea

Chair: Prof. Quang Kien Trinh, LQDTU

14:30-14:55

Coffee break & Expo

14:55-16:07

Session R3: 4 papers/72 min

FPGA and Embedded Systems 1

Chairs: Vu Hoang Gia, LQDTU

Optimizing Quartznet and Conformer Models for Real-Time Vietnamese Speech Recognition on Edge Devices for Autonomous Vehicles

Thanh-AN Luong (Vietnam National University, Hanoi, Vietnam); Huyen-Trang Nguyen-Thi (The University of Da Nang, Vietnam); Duy-Hieu Bui (Vietnam National University, Hanoi, Vietnam); Xuan-Tu Tran (VIetnam National University, Hanoi, Vietnam)

A Lightweight, High-Throughput True Random Number Generator on FPGA Using an RTL-Optimized Elias Extractor

Hieu Nguyen (PTIT University, Vietnam); Hop Quynh Pham (Posts and Telecommunications Institute of Technology, Vietnam); Huyen Thanh Dao (Posts and Telecommunications Institute of Technology, Vietnam & Gunma University, Vietnam)

A Portable Field-Inspection Workflow for Color- and Structure-Faithful Enhancement of PCB Photographs on SBC

Le Tien Hung, Nguyen Huu Tho and Nguyen Le Van (Le Quy Don Technical University, Vietnam)

Dual-Head Incremental Object Detection on Embedded Vision Platforms

Tsung-Han Tsai and Yao-Chieh Tseng (National Central University, Taiwan)

Session R4: 4 papers/72 min

Analog/Mixed-Signal Circuits 1

Chairs: Pham Xuan Thanh, HaIU

A 16 Gbps High-Speed Receiver with Active-Inductor-Based Continuous-Time Linear Equalizer on 14nm CMOS Process

Lê Nguyễn Lam Trường (The University of Science, Ho Chi Minh City, Vietnam); Trần Đức Hồng Quân (Synopsys Vietnam, Vietnam); Nguyen Vu Nhat Hoang (Synopsys Viet Nam, Vietnam); Hung Le Duc (University of Science, VNU-HCM, Vietnam)

A Dual-Channel 6-bit 10-GS/s DAC Design for Driving Forward-Biased MZMs in PNN Prototyping Using 7-nm FinFET Technology

Pradyumna Vellanki (National Sun Yat-Sen University, Taiwan); Chen-Wei Yen (National Sun Yat-sen University, Taiwan); L S S Pavan Kumar Chodisetti and Chua-Chin Wang (National Sun Yat-Sen University, Taiwan)

A Flipped Voltage Follower Based Capacitor-less LDO with gm-Feedforward Compensation and Slew-rate Enhancement

Minh-Tuan Nguyen (VNU University of Engineering and Technology, Vietnam); Duong Huu-Truong and Mai-Huong Nguyen Thi (Vietnam National University Hanoi, Vietnam); Tuan Anh Mai (VNU University of Engineering and Technology, Vietnam); Linh Mai (University of Engineering and Technology, VNU-Hanoi & UET, Vietnam)

A P-SSHI Interface for Piezoelectric Energy Harvesting with an Output-Power-Evaluation MPPT Achieving 98.8% MPPT Efficiency

Zhongxin Ye, Rui Zhang and Jianping Guo (Sun Yat-sen University, China)

16:10-17:40

Session R5: 5 papers/90 min

Hardware Security and Cryptography 1

A DWT-SVD Color Image Watermarking Scheme with Wavelet-GAN-Based Chrominance Reconstruction for Side-Information Reduction

Phuong Nguyen Thu and Thanh Ta Minh (Le Quy Don Technical University, Vietnam)

A High-Speed, Constant-Time, and Memory-Efficient TRNG-Based Sampler for Hamming-Quasi Cyclic KEM

Duc-Thuan Dam (The University of Electro-Communications, Japan); Nguyen Huu Tho (Le Quy Don Technical University, Vietnam); Hung Le Duc (University of Science, VNU-HCM, Vietnam); Cong-Kha Pham (University of Electro-Communications (UEC), Japan)

A Sub-3.82% Native BER Strong PUF Using Power-Gated Diode-Clamped Inverter Chain and Auto-Stabilizing Mechanism in 28nm CMOS

Trung Tien Hoang (Hanoi University of Science and Technology, Vietnam); Dinh Quoc Bao Tran (Chungbuk National University, Korea (South) & ChungBuk National University, Korea (South)); Van Truong Nguyen (Chungbuk National University, Korea (South)); Loan Pham-Nguyen (Hanoi University of Science and Technology & School of Electronics and Telecommunications, Vietnam); Jong-Phil Hong (Chungbuk National University, Korea (South))

An Area-Efficient Polynomial Arithmetic for HQC

Nguyen Tien Hung, Nguyen Huu Tho, Hai Thanh Mai and Quang Nguyen-The (Le Quy Don Technical University, Vietnam); Duc-Thuan Dam (The University of Electro-Communications, Japan)

Hardware-Enforced Security Architecture for Multi-Core RISC-V Systems with Network-on-Chip

Tri-Duc Ta (University of Sciences, VNU-HCM, Vietnam); Van-Quang Vu, Trong-Qui Nguyen, Anh-Quan Le and Nhat-Quang Le (The University of Information Technology, Vietnam); Cong-Kha Pham (University of Electro-Communications (UEC), Japan); Hung Le Duc (University of Science, VNU-HCM, Vietnam)

Session R6: 5 papers/90 min (from RF)

RF & microwave circuits

A 20.2-28 GHz Wide-Tuning Low-Power CMOS LC-VCO with Push-Push Frequency Doubler for FMCW Radar Applications

Juan Salvador (San Jose State University, USA); Mai-Khanh Nguyen (University of Nevada, Las Vegas, USA)

A Wideband Low-Power CMOS Active Mixer with Current-Reused RF Transconductance Enhancement

Khai Van Mai and Tuan Anh Mai (VNU University of Engineering and Technology, Vietnam); Linh Mai (University of Engineering and Technology, VNU-Hanoi & UET, Vietnam)

Compact Quad-Band BPF Based on Four-Stage Folded Open-Loop SIRs for Sub-6 GHz Applications

Thang Van Nguyen (Vietnam National University Hanoi, Vietnam); Cuong Quoc Vuong (Vietnam National University, Vietnam); Nguyen Khanh Huyen (VNU University of Engineering and Technology, Vietnam); Thien Minh Nguyen and Duong Nguyen (International University, Vietnam); Tuan Anh Mai (VNU University of Engineering and Technology, Vietnam); Linh Mai (University of Engineering and Technology, VNU-Hanoi & UET, Vietnam)

A 6 Bit 35-38 GHz Passive Vector-Sum Phase Shifter With Sub-1◦ RMS Phase Error

Dinh-Hung Le and Kim Van Phan (Ho Chi Minh City University of Technology, Vietnam); Sanghun Lee (WAVE PIA, Korea (South)); Cuong Huynh (Ho Chi Minh City University of Technology, Vietnam)

On the Thermal and Voltage Stability of DLS-like Ultra-low-power Ring Oscillators

Dinh Quang Anh (Le Quy Don Technical University, Vietnam); Orazio Aiello (University of Genova, Italy); Van-Phuc Hoang (Le Quy Don Technical University, Vietnam)

18:30-21:00

Gala Dinner

Oct. 09

7:30-8:00

Registration

8:00-8:25

Invited Talk 2: “Open-Source EDA and PDKs in VLSI Design: The Era of Agentic AI, Maturing Ecosystems, and Democratized Silicon”

Prof. Trong-Thuc Hoang, University of Electro-Communications, Japan & Prof. Van-Phuc Hoang, Le Quy Don Technical University, Vietnam

8:25-9:00

Keynote 4: “From Cloud Datacenters to Secure Edge: Review of Compute-in-Memory at EUV/FINFET Era”

Prof. Koichiro Ishibashi, Universiti Teknologi Malaysia Kuala Lumpur (UTMKL), Malaysia

9:00-9:20

Coffee break & Expo

9:20-9:45

Invited Talk 3: A Methodology to Derive Security Specifications for Complex Electronic Systems

Sylvain Guilley (Telecom Paris & Cadence Design Systems, France), Ritu-Ranjan Shrivastwa and Ville Yli-Mayry (Cadence Design Systems, France)

9:50-11:38

Session R7: 6 papers/108 min

AI, Quantum Tech. & Secure Autonomous UxV Systems

Chairs: Prof. Ta Minh Thanh, LQDTU

AI-Enabled Autonomous UxV Navigation via Multi-Sensor Fusion and Risk-Aware Decision Making

Trung Thi Hoa Trang Nguyen and Toan Dao (University of Transport and Communications, Vietnam); Binh Ngo, Thanh (University of Transport and Communications & UTC, Vietnam); Sy Dieu Nguyen (University of Transport and Communications, Vietnam)

Component-wise AST Similarity Metric for Evaluating Text-to-Spatial SQL Models

Thai Hung Vo (Academy of Military Science and Technology, Vietnam); Thanh Chi Nguyen (Institute of Military Science and Technology, Hanoi, Vietnam); Le Thi Thu Hong (Military Institute of Science and Technology & MIST, Vietnam)

HART: Hardware-Aligned Robust Training for Resource-Constrained Edge Device

Chao-Wei Chang, Ya-Chi Peng, Yun-Hao Yang, Wan-Jung Chen and An-Yeu Wu (National Taiwan University, Taiwan); Mladen Berekovic (Universität zu Lübeck, Germany); Shih-Hsu Huang (Chung Yuan Christian University, Taiwan)

RAFT-SF: Risk-Aware Formation Planning with Safety Filtering for UAV Swarms

Duong Van Dan and Thanh Ta Minh (Le Quy Don Technical University, Vietnam)

APEG-QIM: Blind Quantum Image Watermarking with Block-Size Optimization for Robustness

Tuat Dao Ngoc (Thai Nguyen University of Information and Communication Technology, Vietnam); Thanh Ta Minh (Le Quy Don Technical University, Vietnam); Trung-Nghia Phung (Thai Nguyen University of Information and Communication Technology, Vietnam)

Low-Cost Real-Time 3D Environment Perception Using Monocular Depth Estimation on Edge NPU

Quoc-Dat Tran and Duy-Hieu Bui (Vietnam National University, Hanoi, Vietnam); Xuan-Tu Tran (VIetnam National University, Hanoi, Vietnam)

Session R8: 5 papers/90 min

FPGA and Embedded Systems 2

Chairs:

FPGA-based CNN Accelerator for Low-Latency Object Detection Using an Enhanced Systolic Array

Luu Nguyen-Van (Hanoi University of Science and Technology, Vietnam); Nguyen D. Minh (HUST, Vietnam); Xuan Truong Nguyen (Seoul National University, Korea (South)); Dung Viet Do and Linh Nguyen-Thi-Thuy (Hanoi University of Science and Technology, Vietnam); Chi Hoang Phuong (HUST, Vietnam)

MRCA 3.0: Concurrent Post-Quantum and INT8 AI Execution on a Multi-grained Reconfigurable Accelerator

Long Hau Huynh and Tung Lam Truong (Ho Chi Minh City University of Technology and Engineering, Vietnam); Hoai Luan Pham (NARA Institute of Science and Technology, Japan); Huan Minh Vo (Ho Chi Minh University of Technology and Engineering, Vietnam)

Novel High-Speed Pedestrian Detection Using Motion Detection and Object Tracking to Support High-Resolution Video Stream on FPGA

Tuan-Phong Tran (Phenika University, Vietnam); Nam Van Dinh (Phenikaa University, Vietnam); Duy-Hieu Bui (Vietnam National University, Hanoi, Vietnam); Xuan-Tu Tran (VIetnam National University, Hanoi, Vietnam)

Predicting Feasibility and Runtime of Randomized PCA-SVD on Single-Board Computers

Le Tien Hung, Nguyen Le Van and Nguyen Huu Tho (Le Quy Don Technical University, Vietnam)

Radar Pulse Descriptor Word Extraction on RFSoC

Hoang-Gia Vu and Viet-Anh Nguyen-Van (Le Quy Don Technical University, Vietnam); Tuan Khang Nguyen (Center 80 of Electrical Engineerings, Vietnam); Nguyen Tuan (Le Quy Don Technical University, Vietnam)

11:50-13:10

Lunch

13:30-14:05

Keynote 5: “Hardware Accelerator Design and Optimization for Functional Encryption”

Prof. Makoto IKEDA, Systems Design Lab (D.lab), Engineering School, The University of Tokyo, Japan

14:05-15:35

Session R9: 5 papers/90 min

AI, IoT & Communications 2

Chairs:

An Efficient Edge-Device Implementation of 2D ECG Classification Based on the Stockwell Transform and Lightweight Swin Transformer

Thanh-Bao Ho, Minh-Thien Nguyen and Minh-Quang Nguyen (HCMUS, Vietnam); Huu-Thuan Huynh (Ho Chi Minh City - University of Science, Vietnam)

Codebook-Based Synaptic Weight Compression for Spiking Neural Networks

Atharv Sharma and Khanh N. Dang (University of Aizu, Japan)

Improving Hyperdimensional Regression Through Encoder Redesign and Data Augmentation

Sy-Quyen Nguyen (Le Quy Don Technical University, Vietnam); Thi-Nhan Pham (Hanoi University of Science Technology, Vietnam); Quang-Manh Duong, Thi-Nga Dao and Kien Trinh Quang (Le Quy Don Technical University, Vietnam)

Mamba-MK: An Implementation of Mamba Decoding Using a Cooperative Megakernel on Consumer and Edge GPUs

Trinh Thi My Linh (Hanoi University of Science and Technology, Vietnam); Chi Hoang Phuong (HUST, Vietnam); Xuan Truong Nguyen (Seoul National University, Korea (South)); Nguyen D. Minh (HUST, Vietnam)

A lightweight multi-channel CNN for low-latency automatic modulation classification with over-the-air SDR validation

Duong Van Minh (Le Quy Don Technical University, Vietnam & University of Defence, Czech Republic); Giang Phan, Phuong Nguyen, Nguyen Van Dat, Nguyen Van Toi and Pham Trong Hung (Le Quy Don Technical University, Vietnam)

Session R10: 4 papers/72 min

Analog/Mixed-Signal Circuits 2

Chairs:

Adaptive Coincidence Detection with Ambient Photon Statistics for Noise Filtering of d-SiPM-based d-ToF Sensor

Lei Shao, Derun Li and Jianping Guo (Sun Yat-sen University, China)

Foreground Digital Calibration Technique for 14-bit ADC Design Used in PNN Prototyping

L S S Pavan Kumar Chodisetti (National Sun Yat-Sen University, Taiwan); Yen-Jung Lin (National Sun Yat-sen University, Taiwan); Pradyumna Vellanki (National Sun Yat-Sen University, Taiwan); U-Fat Chio (Chongqing University of Posts and Telecommunications, China); Friedel Gerfers (Technical University Berlin, Germany); Chua-Chin Wang (National Sun Yat-Sen University, Taiwan)

Fully Integrated Inductorless Charge Pump for Energy Harvesting Down to 125 mV

Lucas Ott (Technische Universität Dresden, Germany); Jens Wagner (Technische Universität Dresden & Chair for Circuit Design and Network Theory, Germany); Florian Protze and Frank Ellinger (Technische Universität Dresden, Germany)

Co-optimized biasing and ADC architecture for substrate temperature compensation in uncooled IR ROICs

Duong Huu-Truong (Vietnam National University Hanoi, Vietnam); Minh-Tuan Nguyen (VNU University of Engineering and Technology, Vietnam); Mai-Huong Nguyen Thi (Vietnam National University Hanoi, Vietnam); Linh Mai (University of Engineering and Technology, VNU-Hanoi & UET, Vietnam); Tuan Anh Mai (VNU University of Engineering and Technology, Vietnam)

15:35-15:55

Coffee break & Expo

15:55-17:25

Session R11: 5 papers/90 min

Semiconductor Technology

Multi-Cell TCAD Analysis of Parasitic-Bipolar-Effect-Induced Multiple-Cell Upsets in a 12-nm FinFET SRAM

Ryuichi Yasuda (Kyoto University, Japan); Koichi Fukuda and Junichi Hattori (National Institute of Advanced Industrial Science and Technology, Japan); Kozo Takeuchi (Japan Aerospace Exploration Agency, Japan); Yuibi Gomi and Masanori Hashimoto (Kyoto University, Japan)

Phase-Informed Machine Learning for In-Sn-Cu Low-Temperature Solder Alloys: CALPHAD Augmentation, Gaussian Process Regression With Physics, and SHAP-Derived Design Rules

Anh The Vu (Hanoi University of Science and Technology, Vietnam); Chau Van Tran (Le Quy Don Technical University, Vietnam); Han Le Duy (Hanoi University of Science and Technology, Vietnam)

Device-Aware Design and Evaluation of an Ancilla-Assisted Photonic CZ Gate Using Real Mach-Zehnder Interferometer Transfer Matrices

Vu Le Ha (Academy of Science and Technology for Military, Vietnam); Hong Thu Thi Luu (Institute of Electronics, Vietnam); Thanh Cong Pham and Thai Nguyen (AMST, Vietnam)

A Line-Based Adaptive Body-Bias Framework for Low-Power SRAM in 22FDX Technology

Lingfan Zhang (Nanyang Technological University, Singapore); Bah Hwee Gwee (NTU, Singapore)

Physics-Guided Latent-Space Enhancement for Lift-off-Robust Pulsed Eddy Current Corrosion Imaging

Ngo Tung Duong, Ba Long Nguyen, Thang Nguyen Trong and Pham Phuong Huy (Phenikaa University, Vietnam)

Session R12: 4 papers/72 min

Hardware Security and Cryptography 2

An Efficient SoC-FPGA Based Architecture for the Latest ASCON Lightweight Cryptography with Hardware-Software Co-Design

Minh-Thien Nguyen (HCMUS, Vietnam); Bao Thuong T Cao (University of Science, VNU-HCM, Vietnam); Thanh-Bao Ho and Minh-Quang Nguyen (HCMUS, Vietnam); Cong-Kha Pham (University of Electro-Communications (UEC), Japan); Huu-Thuan Huynh (Ho Chi Minh City - University of Science, Vietnam)

An FPGA-Based ECDSA P-256 Key Generation Accelerator with Integrated TRNG

Phuc-Phan Duong (The University of Electro-Communications, Japan); Thanh Ngoc and Hieu Minh Nguyen (Academy of Cryptography Techniques, Vietnam); Trong-Thuc Hoang (The University of Electro-Communications, Japan); Ngoc-Quynh Chu-Thi (Academy of Cryptography Techniques, Vietnam)

Application - Specific Integrated Circuit (ASIC) Implementation of Blowfish Algorithm with Optimized Round and S - Box for Enhanced Performance Using Skywater 130 nm CMOS Process

Agustin G. Carillo, Rommel J. Gumata and Re-Ann Cristine O. Calimpusan (Caraga State University, Philippines); Anastacia B Alvarez (University of the Philippines Diliman, Philippines); Angelo T. Batausa (Caraga State University, Philippines)

FPGA-Based Hardware/Software Co-Design for Modular Reduction and Polynomial Vector Arithmetic in Dilithium scheme

Nhu-Quynh Luc, Phan Cong-Tien-Doan, Nguyen Hai-Long and Nguyen Gia-Bao (Academy of Cryptography Techniques, Vietnam); Thang Nguyen and Toan Dao (University of Transport and Communications, Vietnam)

17:25-17:35

Closing

Oct. 10

9:30-11:00

Committee Meeting

12:00-18:00

Field trip