Invited Speakers

Invited Talk #1: Survey of ML Applications in Function Verification

Michael Chiang
Siemens EDA

Abstract: How the existing ML technologies help on the design function verification and also how can we do better and leverage on the ML for speed up the verification flow and accuracy. What is our next for the on ML for verification.

Biography: Michael Chiang is an Deputy Director at Siemens EDA coving the PacRim front end verification solutions. Michael has more than 20 years of the experience in the IC design house and EDA venders, joined Siemens EDA in 2016 from Cadence as the AE manager for DVT PacRim. Michael is a member of the DVCON Technical committee in Taiwan for the Design Verification area.

Invited Talk #2: Ultra-Low Power Neural Network Processors using Analog-Based Computation

Hiroshi Fuketa
National Institute of Advanced Industrial Science and Technology (AIST), Japan

Abstract: In this paper, two types of low power and energy efficient neural network (NN) inference processors are introduced. First, an energy efficient accelerator for convolutional neural networks (CNNs) using lookup tables (LUTs) based on the vector quantization (VQ) technique is shown. VQ requires a nearest neighbor search (NNS), resulting in a large energy overhead. To overcome this issue, a time-domain associative memory (TAM) using analog-based computation is proposed. Thanks to energy efficient NNS by TAM, the proposed LUT-based CNN accelerator achieves 7.5 times higher efficiency compared with the conventional accelerators. Then, an ultra-low power NN-based audio feature extractor for keyword spotting (KWS) is demonstrated. In the conventional KWS processors, the large portion of the power of the KWS system is consumed in an analog-to-digital converter (ADC) for feature extraction. To tackle with this issue, a NN-based feature extractor is proposed in this work. It extracts audio features in analog-domain, which can remove the power-hungry ADC. Consequently, the power dissipation of the feature extraction can be reduced by -88%.

Biography: Hiroshi Fuketa (Member, IEEE) received the B.E. degree in electrical and electronic engineering from Kyoto University, Kyoto, Japan, in 2002, and the M.E. and Ph.D. degrees in information systems engineering from Osaka University, Osaka, Japan, in 2008 and 2010, respectively. From 2010 to 2015, he was a Research Associate with the Institute of Industrial Science, The University of Tokyo, Tokyo, Japan. Since April 2015, he has been with the National Institute of Advanced Industrial Science and Technology (AIST), Ibaraki, Japan. His research interests include the circuit design of AI chips and cryogenic CMOS circuits for quantum computers.

Invited Talk #3: Activities for Open-Source Integrated Circuits Design in Japan

Akira Tsuchiya
The University of Shiga Prefecture, Japan

Abstract: This paper discusses open-source IC design. By open-source PDKs and EDA tools, IC design is experiencing big change. Conventionally, barrier to entry IC design is quite high. Open-source PDKs and EDA tools democratize IC design to all people. Many benefits are expected in research, industry, education, and so on. However, open-source IC communities are still not mature. This paper explains Japanese communities and activities for open-source IC design. In Japan, we emphasize participation of non-expert people. Some knowledge through challenging tape-out of custom analog IC is introduced.

Biography: Akira Tsuchiya received the B.E., M.E. and Ph.D degrees in Communications and Computer Engineering from Kyoto University, Kyoto, Japan, in 2001, 2003, and 2005, respectively. Since 2005, he has been an Assistant Professor in the Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University. His research interest includes modeling and design of on-chip passive components of high-frequency CMOS, and high-speed analog circuit design. He is a member of the IEICE.

Invited Talk #4: Microwave and Millimeter Wave Rectennas with Gated Anode Diode and Diode on Antenna Topologies

Naoki Sakai
Kanazawa Institute of Technology, Japan

Abstract: This paper presents rectenna topologies that are diode on antenna (DoA) for highly-efficient rectification and gated anode diode (GAD) for high-power one. First of all, DoA topology with a high-impedance dipole antenna including all of RF circuit functionalities is discussed for highly efficient rectification in 5.8 GHz band. The rectifier diodes are directly connected to the antennas without lossy circuit components. In the next discussion, for high-power operation in 5.8 GHz band, a gated anode diode (GAD) configured with gate-drain connected GaAs E-pHEMT is demonstrated for the rectifier instead of GaAs SBD. Finally, DoA topology with a wire-loop antenna is demonstrated for highly efficient rectification in 28 GHz band. In addition, the antenna configuration realizes high radiation gain with the wire and inductive impedance for DoA topology with the loop. It eliminates circuit loss which is more serious in the millimeter wave band.

Biography: Naoki Sakai (Member, IEEE) received the B.E. degree in information engineering and the Dr. Eng. degree in electronic and information engineering from the Toyohashi University of Technology, Aichi, Japan, in 2006 and 2013, respectively. From 2014 to 2019, he was an Assistant Professor at the Department of Electrical and Electronic Information Engineering, Toyohashi University of Technology, Japan, where engaged in the research and development of capacitive wireless power transfer systems and wireless secret key agreement systems. Since 2019, he has been a Researcher with the Center for Electric, Optic, and Energy Applications, Kanazawa Institute of Technology. His current research interests include microwave technologies for microwave power transfer and RF energy harvesting. He is a member of IEICE.