Invited Speakers

Invited Talk #1: Bridging the Gap Between Specification and Reality: Cellular Modem Development and Global Field Testing

Chaehag Yi
Seoul National University, Seoul Korea

Abstract: As wireless communications evolve from 5G-Advanced toward 6G, the cellular modem remains one of the most sophisticated components in modern communication systems. Its primary challenge is to bridge the gap between 3GPP specifications and the unpredictable behavior of real-world wireless environments. This invited talk provides a comprehensive overview of the modem development lifecycle, from algorithm design and silicon implementation to global field testing and future 6G architectures. The presentation examines the pre-silicon and post-silicon development processes. It introduces the hardware/software co-design of baseband SoCs, together with real-time processor clusters that execute L2/L3 protocol stacks. It also discusses the use of link-level simulators and FPGA-based emulation platforms. The post-silicon phase focuses on silicon bring-up, functional verification, and the transition from laboratory debugging to initial over-the-air calibration. Although conformance testing and channel emulation using commercial test systems are essential for validating compliance with 3GPP standards, they cannot fully reproduce the stochastic behavior of operational mobile networks. Modern field testing which includes drive testing, walk testing, and carrier acceptance testing remains indispensable for commercial deployment. Representative field challenges are also introduced to illustrate why real-world validation remains irreplaceable. We discuss the future evolution of modem engineering for the 6G era. Emerging technologies such as AI-native air interfaces, sub-THz communications, and Non-Terrestrial Networks (NTN) will require a fundamental shift from conventional modem architectures toward AI-assisted adaptive systems. By contrasting deterministic laboratory validation with the complexities of real-world deployment, this presentation provides practical insights into the engineering principles required to design, verify, and optimize next-generation cellular modems.

Biography:

Chaehag Yi received the B.S., M.S., and Ph.D. degrees in Electronics Engineering from Seoul National University, Korea, in 1989, 1991, and 1996, respectively. He began his career at ETRI, working on CDMA technology, and later co-founded EoNex, where he developed WCDMA and LTE solutions. During his tenure at Samsung Electronics’ System LSI Business, he served as a Vice President, leading the development of smartphone modem chipsets across WCDMA, LTE, and 5G technologies. He joined the Ministry of Science and ICT (MSIT), Korea, where he was in charge of national R&D planning and management in future communications and radio technologies. He is currently a Visiting Professor in the Department of Next-generation Semiconductor Convergence at Seoul National University, teaching semiconductor systems and AI hardware design. His research interests include wireless communications, cellular modem architectures, semiconductor systems and AI hardware design.

Invited Talk #2: Open-Source EDA and PDKs in VLSI Design: The Era of Agentic AI, Maturing Ecosystems, and Democratized Silicon

Trong-Thuc Hoang
University of Electro-Communications, Japan
**Van-Phuc Hoang
*Le Quy Don Technical University, Vietnam

Abstract: The semiconductor industry continues to experience a profound transformation driven by the open-source hardware movement. Over the past year, the landscape of open-source Electronic Design Automation (EDA) and Process Design Kits (PDKs) has matured rapidly, transitioning from experimental toolchains to robust, community-driven ecosystems. In this talk, we will explore the latest advancements in open-source VLSI design, including the evolution of foundational RTL-to-GDSII flows from OpenLane to LibreLane, and the expansion of accessible fabrication through new open PDKs like IHP 130nm BiCMOS.

Furthermore, we will highlight the most disruptive shift in recent EDA research: the integration of Large Language Models (LLMs) and Agentic AI. We will discuss how “language-to-circuit” methodologies and autonomous AI agents are being integrated into platforms like OpenROAD to automate design, alongside recent benchmarking efforts that reveal the ongoing challenges AI faces in optimizing end-to-end Power, Performance, and Area (PPA). Finally, we will examine how these open-source platforms and subsidized tapeout programs are successfully democratizing hardware education, lowering the barrier to entry, and training the next generation of semiconductor engineers to overcome the industry’s critical talent shortage.

Biography:

Trong-Thuc Hoang received a B.Sc. degree and an M.S. degree in Electronic Engineering from the University of Science (HCMUS), Hochiminh city, Vietnam, in 2012 and 2017, respectively. In 2022, he graduated from the University of Electro-Communications (UEC), Tokyo, Japan, with a Ph.D. degree in Engineering. From 2012 to 2017, he was a lecturer assistant at HCMUS. From 2019 to 2020, he was a research assistant at UEC. From 2019 to 2022, he was a research assistant at the Cyber-Physical Security Research Center (CPSEC), National Institute of Advanced Industrial Science and Technology (AIST), Tokyo, Japan. Since April of 2022, he has been an assistant professor at the Department of Computer and Network Engineering, UEC, Tokyo, Japan. His research interest mainly focuses on digital signal processing, computer architecture, cyber-security, ultra-low power circuit, and system-on-chip.

Van-Phuc Hoang received PhD degree in Electronic Engineering from The University of Electro-Communications, Tokyo, Japan in 2012. He has worked as postdoc researcher, visiting scholar at The University of ElectroCommunications, Tokyo, Japan, Telecom Paris, France and University of Strathclyde, Glasgow, UK during the period of 2012-2018. He is working as an Associate Professor, Director with Institute of System Integration, Le Quy Don Technical University, Hanoi, Vietnam. He is also serving as Vice Chair in International Affairs & Conferences, Radio-Electronics Association of Vietnam (REV). His research interests include hardware security, digital circuits and systems, embedded systems for Internet of Things, and VLSI architecture for digital signal processing. He was the PI of 02 NAFOSTED funded projects and one World Bank funded project in hardware security. He was the Technical Program Chair of several IEEE international conferences such as ICDV 2017, MCSoC 2018, SigTelCom 2019, APCCAS 2020, ATC 2020, ICICDT 2022 and ICD 2026. He is a member of IEEE.

Invited Talk #3: A methodology to derive security specifications for complex electronic systems

Sylvain Guilley
Telecom Paris & Cadence Design Systems, France
Ritu-Ranjan Shrivastwa and Ville Yli-Mayry
Cadence Design Systems, France

Abstract: Today’s electronic systems are becoming increasingly complex; this challenge comes with demanding PPAs. Consider for instance artificial intelligence chips, aiming at datacenters running LLMs or at automotive perception, which manipulate massive data streams. Let aside performance, those systems are also expected to be more and more dependable. Indeed, when electronic systems are based on chiplets, for instance, the supply chain gets longer and therefore brings a larger number of threats. Also, those systems are very versatile, in that they can run varied multi-tenant applications. Therefore, defining what security features are required in this context with numerous stakes is not trivial. Existing scholarly research is very relevant when the security problem is well defined. The resulting scientific papers accordingly dig very deep: this modus operandi has proved productive in exploring new problems, and actually allowed to come up with innovative solutions. For instance, in the field of side-channel attacks, varied mitigations alongside with metrics to evaluate them have been devised. Increasing sophistication resulted from this research, as external considerations have been injected into the problem (typically, aspects such as attack order, impact of combinatorial glitches, etc.). Therefore, we face today the question of selecting the most suitable technology amongst the state of the art proliferation. In addition, in complex systems, we encounter another problem, namely that of defining the security problem(s). A fruitful approach in this respect is a risk based approach. Specifically, the application of a risk-oriented methodology allows to reason on the security rationale. It proceeds as follows. First, the system missions are listed. Then for each of them, the necessary assets are deduced. A threat analysis allows to identify how assets are threatened, and eventually, security requirements can be enunciated. At this stage, the task of matching relevant countermeasures becomes straightforward. In this paper, we give the example of the security specifications for datacenter and automotive chiplets. The considered missions are (secure) provisioning, trimming, debugging, booting, and remote attestation.

Biography:

Sylvain Guilley is a fellow at Cadence, within the Silicon Solution Group. Before this position, he was co-founder & CTO at Secure-IC, a company acquired by Cadence Design Systems in 2025. Sylvain is also an adjunct professor at Telecom Paris, and research associate at Ecole Normale Superieure (ENS). He is lead editor of international standards, such as ISO/IEC 20897 (Physically Unclonable Functions), ISO/IEC 20085 (Calibration of non-invasive testing tools), and ISO/IEC TR 24485 (White Box Cryptography). As administrator of Embedded France professional association, he leads the cybersecurity working group. Sylvain has co-authored 350+ research papers and filed 40+ invention patents.