Program

The 2026 IEEE 11th International Conference on Integrated Circuits, Design and Verification (ICDV 2026)

Hanoi, Vietnam, October 8-10, 2026

Table of Contents

Program at a Glance

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Room: Hoan Kiem

Room: Ba Dinh

Time (Hanoi)

Oct. 08

7:30-8:30

Registration

8:30-8:50

Opening Session

8:50-9:25

Keynote 1: “Next-Generation IC Security: Resilient Hardware Design and AI-Enabled Forensic Verification”

Prof. Bah-Hwee Gwee, Nanyang Technological University, Singapore

9:25-10:00

Keynote 2: “Enforcing Security in the Supply Chain of Chiplets through Transparency”

Dr. Sylvain Guilley, Cadence Design Systems and Telecom Paris, France

10:00-10:25

Coffee break

10:25-11:55

Session R1: 5 papers/90 min

Memory, digital systems and testing

Session R2: 5 papers/90 min

AI, IoT & communications 1

12:00-13:20

Lunch

 

13:30-14:05

Keynote 3: “Practical Non-Destructive Detection: Case Study of Durain, Mangosteen, and Granular Ingredients”

Prof. Kosin Chamnongthai, King Mongkut’s University of Technology Thonburi, Thailand

14:05-14:30

Invited talk 1: Bridging the Gap Between Specification and Reality: Cellular Modem Development and Global Field Testing

Prof. Chaehag Yi, Seoul National University, Korea

14:30-14:55

Coffee break

14:55-16:07

Session R3: 4 papers/72 min

FPGA and Embedded systems 1

Session R4: 4 papers/72 min

Analog/mixed-signal circuits 1

16:10-17:40

Session R5: 5 papers/90 min

Hardware security and cryptography 1

Session R6: 5 papers/90 min

RF, Microwave circuits and related topics

18:30-21:00

Gala Dinner

 

 

Oct. 09

7:30-8:00

Registration

8:00-8:25

Invited Talk 2: “Open-Source EDA and PDKs in VLSI Design: The Era of Agentic AI, Maturing Ecosystems, and Democratized Silicon”

Prof. Trong-Thuc Hoang, University of Electro-Communications, Japan & Prof. Van-Phuc Hoang, Le Quy Don Technical University, Vietnam

8:25-8:50

Invited talk 3: A Methodology to Derive Security Specifications for Complex Electronic Systems

Sylvain Guilley (Telecom Paris & Cadence Design Systems, France), Ritu-Ranjan Shrivastwa and Ville Yli-Mayry (Cadence Design Systems, France)

8:50-9:25

Keynote 4: “From Cloud Datacenters to Secure Edge: Review of Compute-in-Memory at EUV/FINFET Era”

Prof. Koichiro Ishibashi, Universiti Teknologi Malaysia Kuala Lumpur (UTMKL), Malaysia

9:25-9:45

Coffee break

9:45-11:40

Invited talk 4: “Phase measuring deflectometry: A full-field and high-accuracy 3D optical metrology technique for advanced packaging process” (25 min)

Dr. The-Manh Nguyen, Nexensor

Session R7: 5 papers/90 min

FPGA and Embedded Systems 2

Session R8: 6 papers/108 min

AI, Quantum Tech. & Secure Autonomous UxV Systems

11:50-13:10

Lunch

 

13:15-13:50

Keynote 5: “Hardware Accelerator Design and Optimization for Functional Encryption”

Prof. Makoto IKEDA, The University of Tokyo, Japan

13:50-14:25

Keynote 6: “Advances in Energy-Efficient Always-On AI Accelerator Architectures - From Battery-Powered to Purely-Harvested Systems”

Prof. Massimo Alioto, National University of Singapore

14:25-14:45

Coffee break

14:45-16:15

Session R9: 5 papers/90 min

AI, IoT & communications 2

Session R10: 5 papers/90 min

Analog/mixed-signal circuits 2

16:15-17:27

Session R11: 4 papers/72 min

Semiconductor Technology

Session R12: 4 papers/72 min

Hardware security and cryptography 2

17:30-17:40

Closing

 

 

Oct. 10

9:30-11:00

Committee Meeting

Conference venue: 5F, S1 building, Le Quy Don Technical University, 236 Hoang Quoc Viet str., Nghia Do ward, Hanoi, Vietnam
Restaurant for Gala Dinner: Ruby 2 Hall, Trống Đồng Palace, no. 72 Tran Dang Ninh, Nghia Do ward, Hanoi.

Time for presentations:

  • Keynotes: 30 min for presentation and 5 min for Q&A
  • Invited talks: 20 min for presentation and 5 min for Q&A
  • Regular papers: 14 min for presentation and 4 min for Q&A

Notes:

  • Please copy your presentation slides to the laptop at the session rooms before your sessions.
  • All foreigner participants must be with the passports to enter the conference venue.