Keynote #1 Survey and Exploration of Advancements in Hardware Neural Computing

Prof. Oscal Tzyh-Chiang Chen
National Chung Cheng University, Taiwan

Abstract: With the growing demand for efficient computation in various Artificial Intelligence (AI) tasks, hardware neural computing has emerged as a pivotal field of research. This presentation offers a survey and analysis, navigating through the trajectory of past endeavors, recent breakthroughs, and prospective pathways in the realm of hardware designs tailored for neural computing. The hardware designs in neural computing are addressed by examining cell units, modules, architectures, systems, and applications. These facets are realized through the implementation of diverse technologies, including analog circuits, digital circuits, mixed-mode circuits, Field-Programmable Gate Arrays (FPGAs), computing-in-memory, and more. Especially, biologically-inspired neural networks and dedicated neuromorphic hardware are explored as well. Beyond conventional hardware, this talk delves into the latest innovations and emerging technologies that stretch the limits of neural computing across a diverse spectrum of applications.

Biography: Oscal Tzyh-Chiang Chen (Senior Member, IEEE) received a B.S. degree in electrical engineering from National Taiwan University in 1987, and M.S. and Ph.D. degrees in electrical engineering from the University of Southern California, Los Angeles, USA, in 1990 and 1994, respectively. He worked with the Computer Processor Architecture Department, Computer Communication & Research Laboratories (CCL), Industrial Technology Research Institute (ITRI), serving a system design engineer, project leader, and section chief from 1994 to 1995. He was an associate professor with the Department of Electrical Engineering, National Chung Cheng University (NCCU), Chiayi, Taiwan, from September 1995 to August 2003. He also served as the Director of the Academic Development Division, Office of Research and Development, NCCU, from July 2001 to July 2004, and the Director of the Technology Transfer Center, NCCU, from July 2003 to July 2004. Since August 2003, he has been a Professor with the Department of Electrical Engineering, NCCU, in which he served as the Department Chair from August 2018 to July 2021. He was a visiting scholar with the Department of Electrical and Computer Engineering, Carnegie Mellon University, USA, from December 2007 to May 2008, and the Department of Electrical and Computer Engineering, University of Wisconsin-Madison, USA, from February 2011 to July 2011. He has published more than 180 journal and conference papers and five book chapters, and holds 36 Taiwan patents, 22 U.S. patents, and one Chinese patent. His research interests include multimedia processing and understanding, neural networks, VLSI systems, and communication systems. He is a life member of the Chinese Fuzzy Systems Association. In the technical society, he was an Associate Editor of IEEE Circuits and Devices Magazine, from August 2003 to December 2006, and a founding member of the Multimedia Systems and Applications Technical Committee of IEEE Circuits and Systems Society. He also participated in the technical program committees of many IEEE international conferences and symposiums. Prof. Chen has been listed among world’s top 2% of most-cited scientists by Stanford University Ranking in the category of career-long impact (1960-2020~2022) (Scopus).

Keynote #2 Secured Network-on-Chip (SoC) Framework for RISC-V Computer System

Trong-Thuc Hoang, Binh Kieu-Do-Nguyen, and Cong-Kha Pham
University of Electro-Communications (UEC), Tokyo, Japan

Abstract: The new generation of CPUs is anticipated to rely on parallel processing, application-specific supported accelerators and tiled-based architecture. They play a crucial role in addressing the ever-increasing computational requirements and optimizing energy efficiency. The fundamental infrastructure of this talk is an efficient Network-on-Chip (NoC) using RISC-V Instruction Set Architecture (ISA). The objective of this study is to leverage the capabilities of RISC-V to establish a novel architecture for NoC systems, thus aiming to create a framework for developing a multi-core processor based on RISC-V. The final product is a RISC-V NoC that capable of customizing and integrating application-oriented accelerators suitable for each specific application. The framework also integrates the ability to customize enhanced security for applications requiring different levels of security. Additionally, we also implement a new data processing model in the proposed architecture, which is classified into three models: Single-threaded Single-Data, Multi-threaded Single-Data, or a combination of both, called hybrid model. This technology can meet high performance requirements for big data tasks. Finally, the completed system features a secure infrastructure to protect against a multitude of potential threats. Our research aims to propose an innovative approach to address existing challenges in many-core computing systems and meet the growing needs of high-performance computing systems.

Keynote #3 Online ASR and ICA for EEG Signal Processing: Algorithm, Architecture, and Implementation

Prof. Lan-Da Van
National Yang Ming Chiao Tung University, Taiwain

Abstract: It is known that the limited memory resource is a challenge to many offline processing algorithms. In this talk, the hardware-oriented memory-limited online artifact subspace reconstruction (HMO-ASR) and hardware-oriented memory-limited online fast independent component analysis (HMO-FastICA) in terms of algorithm, architecture and implementation for EEG signal processing are addressed. The proposed HMO-ASR algorithm verified by FPGA implementation is composed of 1) two-level window-based preprocessing, 2) iterative mean, standard deviation, covariance matrix update, and 3) early eigenvector matrix determination. The proposed HMO-FastICA algorithm verified by ASIC implementation is composed of 1) garbage detection, 2) channel permutation, and 3) momentum-controlled weight update.

Biography: Lan-Da Van (SM16) received the B.S. (Honors) and the M.S. degree from Tatung Institute of Technology, Taipei, Taiwan, in 1995 and 1997, respectively, and the Ph.D. degree from National Taiwan University (NTU), Taipei, Taiwan, in 2001, all in electrical engineering. Since Feb. 2006, he joined the faculty of the Department of Computer Science, National Yang Ming Chiao Tung University (NYCU), Hsinchu, Taiwan, where he is currently a Professor. From 2021, he serves as an Associate Chief Director of Microelectronics and Information Research Center (MIRC) (First Level Research Center), NYCU. From 2023, he serves as the Director of EECS International Graduate Program (IGP), NYCU. His research interests are VLSI-DSP algorithms, architectures, chips, systems, and applications. This includes the design of low-power/high-performance/cost-effective adaptive filter, computer arithmetic, graphics system, independent component analysis (ICA), machine/deep learning, multi-dimensional filter, and transform. He co-authored the book: Online Component Analysis, Architectures and Applications (now, 2022). The citation count of his publications in Google Scholar is more than 1,550. In 2005, he received the Best Poster Award in the iNEER Conference for Engineering Education and Research (iCEER). In 2014, he received the Best Paper Award in the IEEE International Conference on Internet of Things (iThings). Dr. Van served as a Chairman of the IEEE NTU Student Branch in 2000. In 2001, he has received the IEEE Award for outstanding leadership and service to the IEEE NTU Student Branch. He served as an Officer of the IEEE Taipei Section (2009~2010). Currently, he serves as a Chair-Elect/Secretary of the IEEE Circuits and Systems Society (CASS) VLSI Systems and Applications Technical Committee (VSA-TC) (2022~2024). During this term, VSA-TC received 2023 IEEE CASS Outstanding Technical Committee Recognition. He serves as an IEEE CASS representative to the IEEE Council on RFID (2024~Present). In 2018, he served as a Special Session Co-Chair of the IEEE International Conference on Digital Signal Processing (DSP). In 2019, he served as an Area Co-Chair and a Best Paper Award Committee Member of the IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), and a Publicity Co-Chair of the IEEE International System-on-Chip Conference (SOCC). In 2020, he served as a Best Paper Selection Committee Member of the IEEE AICAS, a Tutorial Co-Chair of the IEEE SOCC, and a Technical Program Committee Co-Chair of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). In 2021, he served as a Special Session Co-Chair of the IEEE International Symposium on Circuits and Systems (ISCAS), a Tutorial Co-Chair of the IEEE SOCC, a Special Session Co-Chair of the International SoC Design Conference (ISOCC), and an international steering committee member of the IEEE APCCAS. In 2022, he served as a Special Session Co-Chair of the IEEE AICAS, a Technical Program Committee Co-Chair of the ISOCC, and a Program Co-Chair of the IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). In 2023, he served as a Special Session Co-Chair of the ISOCC, and a Committee Conference Co-Chair of the IEEE MCSoC. In 2024, he serves as a Program Co-Chair of the 35th VLSI Design/CAD Symposium, and a Conference Committee Co-Chair of the IEEE MCSoC. Dr. Van served as an Associate Editor for the IEEE Transactions on Computers (2014~2018), IEEE Access (2018~2022), IEEE Internet-of-Things Journal (2023~2024), and has been serving as an Associate Editor for the ACM Computing Surveys (2020~Present), and IEEE Transactions on Emerging Topics in Computing (2022~Present). He is a Higher Education Academy (HEA) Fellow.

Keynote #4 Restart of Japan Semiconductor and Our Activity on Steep Slope devices and Cryo-CMOS for Quantum Computing

Jiro IDA
Kanazawa Institute of Technology, Japan

Abstract: Japan is again focusing on production and development on the leading edge logic LSI with attracting TSMC fab., founding Rapidus, and so on. I organized a big symposium, titled as “Restart of Japan’s leading edge Logic semiconductor” at last September, as a leader of Si Technology Division in The Japan Society of Applied Physics. I will review the current status of Japan semiconductor with introducing future-scaling on CMOS technology. I will also introduce our research-activity on the ultra low power devices, so called “Steep slope devices” and the newly started Cryo-CMOS for quantum Computing. We have proposed “PN-Body Tied SOI-FET” as a steep slope device which has applied for RF energy harvesting and recently for the neuromorphic device aiming the next AI. Both have researched in Ishibashi-team of JST-CREST program. We are also joining on one of the big quantum computing research-program by NEDO in Japan. I will show the recent research-trend on quantum computing and also show our data on Cryo-CMOS for quantum computing.

Biography: Jiro Ida received the B.S. M.S. and PhD degrees in Applied Physics from University of Tokyo in 1981, 1983 and 1998, respectively. During 1985-2009, he had been in OKI Electric Industry Co. Ltd., where he had leaded the R&D of CMOS Logic devices & integrations, and FD-SOI technology. He moved to Kanazawa Institute of Technology in 2009. Since then, he has been a professor of the department of Electrical and Electronic Engineering. His current research area covers Ultra low power devices, neuromorphic device, RF Energy Harvesting and Cryo-CMOS for quantum computing. He had been served as a Japan PIDS (Process Integration and Device Structure) leader of a ITRS (the International Technology Roadmap for Semiconductors), a program committee member and a conference secretary of VLSI Technology symposium, a program committee member of IEEE SOI conference, a SOI committee member of CMC (Compact Model Council), and an education and a technical program committee member of IEEE EDTM. He has been served as a program committee member of VLSI-TSA and a Japan member of MM (More Moore) working group of IRDS (International Roadmap for Devices and Systems) and is a leader of Si Technology Division in The Japan Society of Applied Physics.

Keynote #5 Hardware accelerator design optimization for PQC algorithms

Prof. Makoto Ikeda
University of Tokyo, Japan

Abstract:: Post-Quantum Cryptography (PQC) algorithms have been proposed and finalized for standardization by NIST and FIPS. This talk will overview proposed algorithms and describe our recent design optimization trials for some of these algorithms, including, Crystals-Kyber/Dillidium, SPHINCS+, and an isogeny-based algorithm.

Biography: Makoto Ikeda, received his BE, ME, and PhD degrees all from Electrical Engineering of the University of Tokyo, in 1991, 1993, and 1996, respectively, He joined the University of Tokyo as a faculty member in 1996, and is now full professor there.

For past 26 years as a faculty member, he belongs to Electrical Engineering for education and research, and VLSI Design and Education Center for chip design platform activities for entire Japanese Universities. His research interests including hardware security, smart image sensor designs, and time-domain signal processing. He has been belonging to numerous international conference activities, including ISSCC, for 18-year as committee member and ISSCC 2021 ITPC Chair, VLSI Symposium for more than 24-year as committee member and 2017 Program Chair and 2019 Symposium Chair, and A-SSCC from the beginning as committee member and 2015 Program Chair, and many others. He served IEEE SSCS Distinguished Lecturer in 2015 and 2016, and one of Commemorative Lecturers for Transistor 75th Anniversary this year. He is a Senior member of IEEE.

Keynote #6 Novel IC solutions for batteryless and low-cost distributed sensor nodes

Dr. Orazio Aiello
University of Genova, Italy

Abstract: The vision of a world where pervasive integrated electronic systems are fully interconnected to collect, process, and exchange information leads to a significant growth trend in the global smart sensor market. However, powering Internet of Things (IoT) infrastructures of one trillion nodes with batteries poses considerable maintenance and management costs. In the framework of this increasing trend, this tutorial will highlight innovative circuital and systems-level strategies and techniques to drastically reduce power consumption and build battery-less and energy-autonomous electronic devices.

The keynote focuses on the low-cost and low-power consumption requirements for energy-efficient IC design. These demand a small area, low design effort, digital-like shrinkage across CMOS generations, and design/technology portability. Moreover, the possibility to exploit the digital (automated) design flow even for analog building blocks can dramatically reduce the design effort of any system-on-chip enabling aggressively supply-voltage scaled and/or regulator-less building blocks that can be powered directly from energy harvesters.

Biography: Orazio Aiello (Senior Member, IEEE) received the B.Sc. and M.Sc. degrees (cum laude) from the University of Catania, Italy, in 2005 and 2008, respectively, the M.Sc. degree (cum laude) from Scuola Superiore di Catania, Italy, in 2009, and the Ph.D. degree from Politecnico di Torino, Italy, in 2013. He was a Mixed Signal IC Designer and an EMC Consultant with STMicroelectronics, Castelletto, Italy, from 2008 to 2009, and NXP-Semiconductors, Nijmegen, The Netherlands, in 2014. From 2015 to 2021, he was with the Green IC Group, National University of Singapore. He is/was the leader/coordinator of a few EU-funded projects (i.e. ULPIoT, UBIGIoT). He is currently a tenure-track Assistant Professor at the University of Genoa, Italy. His main research interests include energy-efficient analog-mixed signal circuits and sensor interfaces. He is/was a Technical Program Committee member of several conferences, such as NORCAS and APCCAS. He is an IEEE CASS Distinguished Lecture (2024-2025). He is an Associate Editor of IET Electronics Letters and the International Journal of Circuit Theory and Applications (Wiley). He serves as a regular reviewer for several IEEE journals.