Keynotes

Keynote #1: Enforcing security in the supply chain of chiplets through transparency

Sylvain Guilley
Cadence Design Systems and Telecom Paris, France

Abstract: In an open market, a massive amount of chiplets will arise from various provenances. How to ascertain that they are genuine? How to ensure that they won’t be counterfeited? In this presentation, I will advocate that ecosystem coordination is required. Trust in the chiplets model requires that IP can be traced. Hence, the need for an industry-level transparency in the sourcing. For such a vision to become concrete, chiplets shall be considered as roots of trust. Concrete solutions will be put forward, building on open standards.

Biography: Sylvain Guilley is a fellow at Cadence, within the Silicon Solution Group. Before this position, he was co-founder & CTO at Secure-IC, a company acquired by Cadence Design Systems in 2025. Sylvain is also an adjunct professor at Telecom Paris, and research associate at Ecole Normale Superieure (ENS). He is lead editor of international standards, such as ISO/IEC 20897 (Physically Unclonable Functions), ISO/IEC 20085 (Calibration of non-invasive testing tools), and ISO/IEC TR 24485 (White Box Cryptography). As administrator of Embedded France professional association, he leads the cybersecurity working group. Sylvain has co-authored 350+ research papers and filed 40+ invention patents.

Keynote #2: Next-Generation IC Security: Resilient Hardware Design and AI-Enabled Forensic Verification

Bah-Hwee Gwee
Nanyang Technological University

Abstract: Modern integrated circuits face increasingly sophisticated physical and structural attacks across their lifecycle. This keynote presents a closed-loop approach to hardware security that combines proactive, by-design resilience with automated post-silicon forensic verification. The first half of the talk introduces hardware design-for-security techniques that protect against run-time threats. We present an asynchronous AES engine that integrates dual-rail balanced logic for amplitude hiding with stochastic delay lines for time-domain desynchronization, reducing side-channel leakage from transient physical signatures. We also discuss resilient logic locking techniques, including advanced MUX-based approaches such as N-MUX and InvMUX, which mitigate structural leakage exploited by machine learning-driven reverse engineering and IP piracy attacks. The second half focuses on supply-chain trust and post-fabrication verification. We showcase an intelligent forensic pipeline that combines computer vision and generative AI to analyze high-resolution IC microscopy images for circuit-layer segmentation and automated netlist extraction. Hierarchical Graph Neural Networks (GNNs) are then used to identify functional subcircuits without prior layout knowledge, while BERT-style Masked Language Models (MLMs) support firmware provenance analysis and binary code error correction. By integrating hardware-level protection with AI-driven post-silicon verification, this talk highlights a practical pathway toward establishing trustworthy and verifiable next-generation silicon systems.

Biography: Dr. Bah-Hwee Gwee received his B.Eng degree from University of Aberdeen, UK, in 1990. He received his MEng and PhD degrees from Nanyang Technological University in 1992 and 1998 respectively. He been an Associate Professor in NTU since 2005. He is currently the Associate Chair Undergraduate (Students) in School of EEE, NTU and the Director of National Integrated Center for Evaluation, Singapore. He has been the PIs and Co-PIs of a number of research projects including Singapore NRF, DSO, A*STAR, MoE, DSTA, CSA and USA DARPA with research grants amounting to more than US$15m. He has published more than 200 technical papers, 6 granted US patents and 2 Start-up Companies in 2005 and 2020. His areas of research are in hardware assurance, hardware security and post quantum safe cryptography ICs.

Dr Gwee was the Chairman of IEEE Circuits and Systems Society (CASS) Singapore Chapter in 2005, 2006, 2013 and 2016. He was the Chairman of IEEE CASS DSP Technical Committee (2019-2020). He was the General Chair of IEEE DSP 2018, IEEE SOCC 2019, IEEE ISICAS 2021 and IEEE ISCAS 2024. He is currently the Chair of the IEEE CAS Society Distinguished Lecturer Program since 2025. He had presented keynotes in IEEE PAINE, IEEE APCCAS, IEEE MCSoC, ICDIS and AIPOSH. He has also served as Associate Editors of several journals, including IEEE CAS Magazine (2021-2022) IEEE T-CAS II (2010-2011, 2018-2019 and 2020-2021) and IEEE T-CAS I (2012-2013). He was an IEEE Distinguished Lecturer in 2009-2010 and in 2017-2018. He was awarded the Singapore Defence Technology Prize (R&D) in 2016.

Keynote #3: Hardware Accelerator Design and Optimization for Functional Encryption

Makoto IKEDA
Systems Design Lab (D.lab), Engineering School, The University of Tokyo, Japan

Abstract: This talk covers, hardware accelerator design and optimization of various crypto-algorithms, especially, functional encryption algorithms, including Attribute-based Encryption (ABE). Starting with elliptic-curve and pairing as basis of crypto-algorithms, this talk covers, how to optimize entire functional algorithm implementation in ASIC. This talk also covers, our recent research activities on Agile-X project, which to realize rapid chip design and fabrication.

Biography: Makoto Ikeda received B.E, M.E, and Ph.D. degrees all from Electronic Engineering, the University of Tokyo, in 1991, 1993, and 1996, respectively. He joined the University of Tokyo as a Research Associate in 1996, and is now a Full Professor, in Systems Design Lab.(d.lab), Engineering School, the University of Tokyo. He has been deeply engaged in the VLSI Design and Education Center (VDEC) activities, which is chip design platform for entire Japanese academia, from its foundation of 1996, and is now a director of d.lab, as well as a director of TSMC-Utokyo Lab, and a special advisor to the President of the University of Tokyo. He served a Science Advisor to the Ministry of Education in 2024 and 2025. He served numerous positions in numerous conferences, including ISSCC 2021 ITPC Chair, VLSI Circuits Symposium 2019/17 Symp. And TPC Chairs, A-SSCC 2015 TPC Chair, and ASP-DAC 2027 General Chair. He is now a Vice-President of IEEE Solid-State Circuits Society, and President-Elect of IEICE, Engineering Sciences Society. He is a Senior member of IEEE and Fellow of IEICE.

Keynote #4: From Cloud Datacenters to Secure Edge: Review of Compute-in-Memory at EUV/FINFET Era

Koichiro Ishibashi
Malaysia - Japan International Institute of Technology (MJIIT),
Universiti Teknologi Malaysia Kuala Lumpur (UTMKL), Malaysia

Abstract: Driven by the massively parallel processing of MAC units in GPUs and the high-bandwidth scaling of memory systems such as HBM, AI training performance has expanded significantly, leading to larger model scales with massive parameter counts. Concurrently, edge devices demand a reduction in circuit area for inference, lower power consumption, and low-bit quantization of integer (INT) and floating-point (FP) data formats to meet form-factor constraints. To achieve the next breakthrough in AI performance against these technological trends, Compute-in-Memory (CIM) and Processor-in-Memory (PIM) technologies have been actively discussed.　In FinFET technologies from the 16nm down to the 3nm node fabricated via EUV lithography, matching the gate pitch between 6T SRAM memory arrays and peripheral logic circuits prevents transistor characteristic degradation even when they are placed in close proximity. This enables compact layout areas for CIM/PIM implementations. Furthermore, FinFETs offer excellent saturation characteristics (low drain conductance Gd), a subthreshold slope close to the theoretical limit, and minimal device variation. Leveraging these features alongside dynamic assist circuits, numerous techniques have been proposed to operate both logic and SRAM at the same scaled low voltage. This invited talk provides an overview of recent PIM/CIM technologies, focusing primarily on the cutting-edge innovations discussed in the 16nm to 3nm generations.

Biography: Prof. Koichiro Ishibashi is currently a Professor of Malaysia - Japan International Institute of Technology (MJIIT), Universiti Teknologi Malaysia Kuala Lumpur (UTMKL), Malaysia. He was a full professor of UEC from 2011 to 2023, where he had investigated on low power IoT systems and Energy harvesting technologies for IoT as well as low power LSI design technologies. He has been serving a visiting professor at Ho Chi Minh City University of Technology and Ho Chi Minh City University of Science since 2012. He also serves a visiting professor at Vietnam National University, Information Technology Institute since 2023. After receiving doctor degree from Tokyo Institute of Technology in 1985, he worked at Central Research Laboratory, Hitachi Ltd. and at Renesas Electronics, where he had investigated low power LSI technologies for high density SRAMs and MCUs. He was awarded R&D 100 for the development of SH4 Series Microprocessor in 1999. He has been a Fellow of IEEE from 2005 for the technical contributions to developments of low-power SRAMs and MCUs, and has been a Life Fellow of IEEE since 2024. Throughout his carrier of R&D and education on semiconductor devices and IC designs for 43 Years, he has presented more than 250 academic papers at international conferences and journals including 30 key note or invited presentations. His current interest is educational activities and training on updated semiconductor technologies and IC design techniques, and IoT technologies.

Keynote #5: Practical Non-Destructive Detection: Case study of Durain, Mangosteen, and Granular Ingredients

Kosin Chamnongthai
King Mongkut’s University of Technology Thonburi, Thailan

Abstract: Many agricultural products such as granular ingredients, durian, mangosteen, and so on need moisture measurement to determine quality. Originally, the moisture inside fruits and granular ingredients are manually measured by percent dry weight which is precise destructive way and takes as long as 24-hour time. Consumers normally prefer non-destructive way which is believed not to destroy agricultural product quality. Technically microwave is sensitive with moisture and selected in this research project to sense moisture for the product quality guarantee. The talk may discuss how to design container and system for granular ingredient, mangosteen, and durian inspection as practical case study.

Biography: Kosin Chamnongthai currently works as a professor at the Electronic and Telecommunication Engineering Department, Faculty of Engineering, King Mongkut’s University of Technology Thonburi (KMUTT). He now serves as president-elect of APSIPA Association (2025-2026), and have served as vice president (conference) of APSIPA Association (2020-2023), president of ECTI Association (2018-2019), editor of ECTI e-magazine (2011-2015), associate editor of ECTI-CIT Trans (2011-2016), associate editor of ECTI-EEC Trans (2003-2010), associate editor of ELEX (IEICE Trans) during 2008-2010, and chairman of IEEE COMSOC Thailand (2004-2007). He received a B.Eng. in Applied Electronics from the University of Electro-communications, Tokyo, Japan in 1985, an M.Eng. in Electrical Engineering from Nippon Institute of Technology, Saitama, Japan in 1987, and a Ph.D. in Electrical Engineering from Keio University, Tokyo, Japan in 1991. His research interests include computer vision, image processing, robot vision, signal processing, and pattern recognition. He is a senior member of IEEE, and a member of IEICE, TESA, ECTI, AIAT, APSIPA, TRS, and EEAAT.