Keynotes

Keynote #1: Advanced Biomedical Imaging Technologies: Circuit Design and Techniques

Yongfu Li
Shanghai Jiaotong University, China

Abstract: Electrical Impedance Tomography (EIT) is transforming biomedical imaging, offering non-invasive, cost-effective solutions for critical healthcare diagnostics. This keynote explores state-of-the-art EIT technologies, emphasizing advanced circuit design and innovative imaging methods. I will present the latest developments in circuit design and imaging techniques, highlighting their impact on diagnostic accuracy and system performance. We will discuss the rising demand for wearable EIT sensors, driven by the urgent need for continuous, real-time monitoring of patient health beyond traditional clinical settings. Attendees will gain insights into practical applications of EIT, equipping them to drive innovation, enhance diagnostics, and significantly improve patient outcomes.

Biography: Yongfu Li (S’09-M’14-SM’18) received the B.Eng. and Ph.D. degrees from the Department of Electrical and Computing Engineering, National University of Singapore (NUS), Singapore, in 2009 and 2014, respectively.

He was a research engineer with NUS from 2013 to 2014. He was a senior engineer (2014-2016), principal engineer (2016-2018), and member of technical staff (2018-2019) with GLOBALFOUNDRIES, as a Design-to-Manufacturing (DFM) Computer-Aided Design (CAD) Research and Development engineer. He is currently an Associate Professor (tenured) in the School of Integrated Circuit Designs at Shanghai Jiao Tong University, China. His research interests include analog and mixed-signal circuits, biomedical signal processing, and circuit automation.

Throughout his career, Dr. Li has received numerous awards for his work. His achievement awards (individual and team) include the International Excellent Young Scientists Award (China) in 2023, the National Thousand Talent Program Award (China) in 2018, the IEEE MGA Young Professionals Achievement Award in 2022, the IEEE R10 Young Professionals Individual Award in 2022, the IEEE Young Professionals Hall of Fame Award in 2021, and the IEEE R10 Young Professionals Team Award in 2015. His academic awards include the IEEE BioCAS 20th Anniversary Top WiCAS-YP Contributor in 2024, IEEE ISCAS Best Live Demonstration Award (1st Place) in 2024, the IEEE PrimeAsia Gold Leaf Certificate in 2022 and 2024, the IEEE ICTA Best Paper Award and Best Paper Nomination Award in 2021 and 2020, 2nd Place in IEEE CVPR Low Power Computer Vision Challenge in 2020, the IEEE ISVLSI Best Paper Nomination Award in 2018, and the Design Contest Award in 20th International Symposium on Low Power Electronics and Design in 2015. His industrial awards include the Best Presentation Award (Overall) in Synopsys User Group Singapore in 2018, the Best Paper Award (Physical Verification) in Synopsys User Group Singapore in 2018, the Outstanding Paper Award in Cadence CDNLive Taiwan in 2018, and the Best Paper Awards in Synopsys Users Group Silicon Valley, Penang, and Singapore in 2017. As an educator, he collaborates closely with the IEEE CAS Society to develop a range of educational programs, and the Society received the IEEE EAB Society/Council Professional Development Award in 2023. Under his guidance in the school, his students received many awards including IEEE CASS Pre-doctoral Award (Qing Zhang, Jiajie Huang, and Chao Wang), IEEE CASS Student Travel Grant (Jiajie Huang, Chao Wang, Wangzilu Lu, Yilun Jin, and Ruoyu Tang), IEEE BioCAS Young Researcher Support Award (Yi Ma), IEEE BioCAS Grand Challenge Research Award (Qing Zhang), National Scholarship (Changyan Chen, Weihong Yan), Shanghai Jiao Tong University Best Undergraduate Dissertation Award (Ting Zhou), and with more than 40 International and National (China) IC design and EDA Contest Awards, such as IEEE CAS Student Design Competition World Winner, China Postgraduate IC Innovation Competition, China College IC Competitions, and Integrated Circuit EDA Elite Challenges.

Dr. Li is an active volunteer in IEEE. He is a Board of Governors (BoG), and R10 Member At Large of the IEEE Circuits and Systems (CAS) Society, an AdCom Members of the IEEE Biometrics Council, a member of the IEEE DataPort Steering Committee, a corresponding member of the IEEE TAB Standard Activities, Chair of the IEEE CASS Standard Activities Sub Division, Chair of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Steering Committee. He has served as the first IEEE CAS Society Board of Governors (BoG) representative for Young Professionals (YP) from 2020 to 2021. He is also involved in several editorial works such as the Associate Editor-in-Chief for IEEE Open Journal of Circuits and Systems (OJCAS) in 2023, the Senior Editor for IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) from 2024 to 2025, and the Associate Editor for IEEE Data Descriptions (2024), IEEE Integrated Circuits and Systems (2024), IEEE OJCAS from 2022 to 2024 and IEEE Transactions on Biomedical Circuits and Systems (TBioCAS) from 2020 to 2025. He also founded the IEEE Singapore and Shanghai Sections YP Affinity Group in 2012 and 2019, respectively. He has been involved in various roles, including General Chair and TPC Chair, in numerous prestigious IEEE flagship conferences (ISCAS, ISICAS, AICAS, NEWCAS, ISVLSI, ASP-DAC, and APCCAS), as well as regional activities.

Keynote #2: Multi-core Multi-thread RISC-V-based System-on-Chip

Cong-Kha Pham
The University of Electro-Communications, Japan

Abstract: The relentless demand for computational power has driven the development of diverse parallel architectures, fundamentally categorized as general-purpose and special-purpose systems. General- purpose systems, characterized by programmable controllers, provide versatility across a wide range of applications. Conversely, special-purpose systems, utilizing fixed hardware controllers, prioritize efficiency for specific tasks. Multicore processors, a cornerstone of modern computing, are employed in both categories, leveraging interconnected functional modules to enable concurrent execution. General-purpose multicore architectures, such as linear arrays and trees, are adept at handling varied workloads, while specialized multiprocessors, including systolic arrays and hypercubes, are tailored to specific computational patterns. Designing these complex systems requires significant expertise to optimize performance and overcome the inherent memory bottlenecks associated with traditional architectures.

The advent of the big-data era has brought about a paradigm shift towards data-centric design, placing a strong emphasis on the importance of high-quality, structured data. This shift has also blurred the traditional boundaries between general-purpose and special-purpose systems, leading to the emergence of hybrid designs that integrate features from both categories. Notable examples include NVIDIA’s GH200 and GB200 architectures, which effectively combine the flexibility of programmability with the efficiency of specialized hardware accelerators.

Furthermore, the importance of hardware/software co-design has become increasingly evident. Modern computing systems are highly complex, requiring a holistic approach where hardware and software are developed in tandem to achieve optimal performance and efficiency. Software frameworks developed by companies like Tenstorrent and Cerebras, alongside custom chips designed by companies like Meta and Microsoft, underscore the significance of integrated design methodologies. These efforts aim to strike a balance between the flexibility of general-purpose systems and the efficiency of application-specific designs.

Our research leverages the RISC-V open-source Instruction Set Architecture (ISA) to develop advanced multicore systems, focusing on both hardware design and multithreaded software. A high- performance core initiates thread generation for non-parallel tasks, storing thread information in a queue accessible by other cores. Upon queue writes, idle cores are activated to fetch and store thread data, mitigating shared resource bottlenecks. Bidirectional private buses are employed to further minimize data movement overhead.

We have explored the integration of near-cache processing capabilities and tightly coupled accelerators, utilizing a hybrid Level 1 (L1) cache. This cache can function as both a traditional cache and local memory, enabling efficient data access for accelerators such as Matrix Processors. Techniques like divide-and-conquer and task splitting are utilized to optimize performance, with minimal hardware overhead.

Software benchmarks, including matrix multiplication and convolution, have demonstrated significant performance gains. Four-core configurations achieve speed-up factors ranging from 4 to 6 times, while eight-core configurations yield speed-ups ranging from 6 to 18 times. The hybrid L1 cache, coupled with tightly coupled accelerators, achieves speed-ups ranging from 6 to over 1,000 times compared to a single core, highlighting the effectiveness of this integrated design approach.